A digital delay locked loop with a monotonic delay line

This paper proposes a digital delay locked loop (DLL) with monotonic line (DL). DLL adopts the calibration mode to reduce non-monotonic effects for coarse-tuning (CTDL) and fine-tuning (FTDL). The detects time of unit, timing resolution CTDL, adjust range FTDL. Thus, can limit overlap between CTDL proposed was implemented using 0.18-μm CMOS process, RMS peak-to-peak jitters were 0.21% 1.72%, respectively, at 560 MHz.